Senior ASIC Timing Engineer

). Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus). Proficiency in Python...

Lugar: Westford, MA | 22/01/2026 01:01:30 AM | Salario: S/. No Especificado | Empresa: Nvidia

Infrastructure Software Engineer

with Familiarity with Bazel build system Deep understanding of ASIC development flows, especially those involving Synopsys, Cadence...

Lugar: San Jose, CA | 20/01/2026 19:01:58 PM | Salario: S/. $15000 - 25000 per year | Empresa: Etched

Power Electronics Research Engineer

: Experience with EDA tools (Cadence, Mentor Graphics, Synopsys), FPGA prototyping, and the Siemens IC portfolio. Domain...

Lugar: Dearborn, MI | 18/01/2026 02:01:40 AM | Salario: S/. $113580 - 190500 per year | Empresa: Ford

R&D Engineer IC Design 4

: · TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler... · Understanding of liberty LIB models for timing · Formal verification (Synopsys Formality / Cadence Conformal) · Spyglass Lint...

Lugar: USA | 16/01/2026 22:01:13 PM | Salario: S/. No Especificado | Empresa: Broadcom