HBM SoC RTL Design Engineer

considerations. Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens. Programming or scripting experience (e.g...

Lugar: Folsom, CA | 01/08/2026 20:08:45 PM | Salario: S/. $121000 - 247000 per year | Empresa: Micron

Senior ASIC Design Engineer

to silicon characterization Very familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal...

Lugar: Vancouver, WA | 30/07/2026 20:07:35 PM | Salario: S/. $116150 - 182400 per year | Empresa: HP