in SystemVerilog and Verilog. Experience working with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens...
, Simulink, synopsys (ANSYS), Sherlock, CFD, FEA, SPICE, MathCAD, or experience in general simulation testing (MIL, SIL, HIL...
and quality. Timing signoff: Perform block-level and full-chip static timing analysis and signoff using Synopsys PrimeTime...-on experience with Synopsys PrimeTime / PrimeTime SI for block and/or full-chip timing signoff. Proficiency in SDC constraint...
and quality. Timing signoff: Perform block-level and full-chip static timing analysis and signoff using Synopsys PrimeTime...-on experience with Synopsys PrimeTime / PrimeTime SI for block and/or full-chip timing signoff. Proficiency in SDC constraint...
: · TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler... · Understanding of liberty LIB models for timing · Formal verification (Synopsys Formality / Cadence Conformal) · Spyglass Lint...
Engineering, Computer Engineering, or related STEM field Experience with Synopsys simulators (e.g., VCS), debug tools...
, or top-level design flow. Familiarity with Synopsys Fusion Compiler or similar next-generation design tools. Hands-on use...
static timing analysis and signoff using Synopsys PrimeTime / PrimeTime SI (and/or Cadence Tempus) across a full multi-mode..., slack, path groups, clock latency, uncertainty, and derating concepts. Hands-on experience with Synopsys PrimeTime...
– Experience supporting semiconductor design and tapeout flows, including Calibre, ASML Brion, Cadence, Synopsys, or similar EDA...
, and upgrade paths for critical hardware and software engineering toolchains (e.g., Cadence, Synopsys, PTC Creo, Azure DevOps...