HBM SoC RTL Design Engineer

considerations. Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens. Programming or scripting experience (e.g...

Lugar: Folsom, CA | 01/08/2026 23:08:27 PM | Salario: S/. $121000 - 247000 per year | Empresa: Micron

Signal Integrity Engineer

HFSS, SIwave, Q3D, Synopsys tools, and related SI/PI analysis environments. Understanding of package and board design...

Lugar: Texas | 01/08/2026 21:08:54 PM | Salario: S/. No Especificado | Empresa: GlobalFoundries

Senior ASIC Design Engineer

to silicon characterization Very familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal...

Lugar: Vancouver, WA | 30/07/2026 19:07:35 PM | Salario: S/. $116150 - 182400 per year | Empresa: HP