Power Electronics Research Engineer

: Experience with EDA tools (Cadence, Mentor Graphics, Synopsys), FPGA prototyping, and the Siemens IC portfolio. Domain...

Lugar: Dearborn, MI | 17/01/2026 20:01:03 PM | Salario: S/. $113580 - 190500 per year | Empresa: Ford

Senior RTL2GDS SD Engineer

on Synopsys OR Cadence tools and Flows. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary...

Lugar: Austin, TX | 17/01/2026 18:01:34 PM | Salario: S/. No Especificado | Empresa: Intel

DFT Engineer

fundamentals. Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite. Proficiency with Perl...

Lugar: USA | 16/01/2026 19:01:36 PM | Salario: S/. $108000 - 172800 per year | Empresa: Broadcom

R&D Engineer IC Design 4

: · TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler... · Understanding of liberty LIB models for timing · Formal verification (Synopsys Formality / Cadence Conformal) · Spyglass Lint...

Lugar: USA | 16/01/2026 18:01:53 PM | Salario: S/. No Especificado | Empresa: Broadcom