R&D Engineer IC Design 4

: · TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler... · Understanding of liberty LIB models for timing · Formal verification (Synopsys Formality / Cadence Conformal) · Spyglass Lint...

Lugar: USA | 16/01/2026 22:01:36 PM | Salario: S/. No Especificado | Empresa: Broadcom

DFT Engineer

fundamentals. Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite. Proficiency with Perl...

Lugar: USA | 16/01/2026 21:01:28 PM | Salario: S/. $108000 - 172800 per year | Empresa: Broadcom

Staff Silicon Design Verification Engineer

of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Strong understanding of state of the art... management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal...

Lugar: San Jose, CA | 14/01/2026 22:01:15 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

FPGA Design Engineer

with Xilinx FPGAs and related toolsets such as Vivado - Experience with FPGA simulation tools and languages such as Synopsys VCS...

Lugar: Orlando, FL | 14/01/2026 00:01:47 AM | Salario: S/. No Especificado | Empresa: Lockheed Martin