Senior Engineer - Design for Test (DFT)

tools like Siemens Tessent or Synopsys TestMax. Knowledge of Verilog or System Verilog with experience using simulators... bring-up with proficiency in Mentor Tessent / Synopsys tools for Yield & Diagnosis. Proactive & self-motivated, eager...

Lugar: Hillsboro, OR | 30/12/2025 21:12:20 PM | Salario: S/. No Especificado | Empresa: Microsoft

ASIC/FPGA Design Engineer (SMES)

has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS... with Synthesis/PAR: SDC, Synopsys Synplify, Vivado Strong logic/board debug, and analytical skills. Experience with project...

Lugar: Camden, NJ | 19/12/2025 18:12:22 PM | Salario: S/. $111515 - 151500 per year | Empresa: L3Harris Technologies
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