from RTL design through structural netlist timing closure including CDC and UPF. 5+ years' experience in schematics design...
better ones. When a customer says their LVS is failing, you dig into whether it is a netlist issue, a rule deck bug, or a layout...
with the ASIC design team to validate UPF at RTL and netlist level using industry standard tools As the implementation lead... constraints. Check the RTL design for clean synthesis run, perform STA and LEC on netlist. Work with RFIC teams to make sure the...
, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent tools for RTL and gate netlist DFT...
Design and Design for Test teams, driving complex customer SoC projects from RTL or Netlist to GDS. These critical SoCs...
, LVS, EM/IR, etc. Gate netlist synthesis Skill Set Required Strong design skills Ability to write and debug Verilog...
you will own DFT insertion, verification, DRC check, and test coverage closure from RTL/netlist through post-silicon debug...
, timing and power convergence, and ECO implementation Ensure clean netlist handoffs and predictable convergence...
;identify and resolve simulation failures, timing issues, X-propagation, and model or netlist mismatches. Own the generation..., netlist, constraint, clocking, reset, timing, and X-propagation issues. Knowledge of zero-delay and SDF-annotated simulation...
from RTL/netlist through post-silicon debug. As a senior member of the DFT team, you will work closely with the architecture... Experience developing and validating scan and test-mode timing constraints End-to-end DFT lifecycle experience, from RTL/netlist...