Senior Emulation Engineer

as experience with compilation, debug, performance testing. Prior experience with RTL development for Emulation prototypes...

Lugar: San Jose, CA | 26/01/2026 18:01:26 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Senior Hardware Engineer- FPGA

of the project. You are an experienced FPGA designer able to write RTL code, run simulations, address timing... Verilog RTL coding Experience with industry leading FPGA devices and tools. Preferred Qualifications Experience with UVM...

Lugar: Milpitas, CA | 26/01/2026 18:01:15 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Design Verification Engineer

implementation and review Qualify RTL design by running Gate Level Simulations on netlists Collaborate with designers, architects... desirable Knowledge of formal verification tools (e.g., Jasper or VC Formal) Experience with RTL Design desirable Familiarity...

Lugar: San Jose, CA | 26/01/2026 18:01:09 PM | Salario: S/. $135800 - 193400 per year | Empresa: Cisco Systems

ASIC Engineer

and coverage for complex chips. You will also design RTL as per the architecture specs. Your collaboration with architects.... You will: Writing testplans Specification and test plan reviews Implementing RTL designs Building test cases, scripts, reference...

Lugar: San Jose, CA | 26/01/2026 18:01:25 PM | Salario: S/. $135800 - 193400 per year | Empresa: Cisco Systems

Hardware FPGA Design Engineer - Acacia (Hybrid)

Contribute to FPGA Emulation of ASIC Blocks Contribute to our custom ASIC RTL code Minimum Qualifications: Bachelors +8... with minimum 5+ years of FPGA design and verification experience Experience in Verilog RTL coding and synthesis for FPGAs...

Lugar: Maynard, MA | 26/01/2026 18:01:01 PM | Salario: S/. No Especificado | Empresa: Cisco Systems