Silicon Design Engineer

following: Developing synthesizable RTL (SystemVerilog / Verilog) for complex digital blocks;Implementing control logic..., datapaths, state machines, and protocol engines;Ensuring RTL adheres to coding guidelines, clocking/reset strategies, and low...

Lugar: San Jose, CA | 27/06/2026 22:06:21 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning

with multiple teams and engineers including architects, RTL designers, Verification engineers, , Physical Design engineers... with ARM and various DSP ISAs - Familiarity with Make or similar for automation of EMIR rollups - Experience with RTL design...

Lugar: Cupertino, CA | 27/06/2026 22:06:58 PM | Salario: S/. No Especificado | Empresa: Amazon

Senior SoC Subsystem and I/O Architect - LPU

interactions before RTL or silicon is available. Drive tradeoffs across bandwidth, latency, power, area, timing, scalability... behavior, verification plans, and validation strategies. Collaborate with architecture, IP, firmware, software, RTL...

Lugar: California | 27/06/2026 22:06:47 PM | Salario: S/. No Especificado | Empresa: Nvidia

Senior Principal Digital Design Engineer

compression, AI/HW accelerators) Analyze standards (PCI-SIG, IEEE 802.3, UALink, etc) and translate into implementable RTL Work... partitioning, and execution plan Lead improvements to design methodology to maximize efficiency and predictability RTL...

Lugar: Carlsbad, CA | 27/06/2026 22:06:14 PM | Salario: S/. $186000 - 228000 per year | Empresa: MaxLinear