Principal Digital IC Design Engineer

’s components. RTL Design and Synthesis: - Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.... - Optimize RTL code for area, power, and performance. - Implement and verify complex digital blocks. Constraint Development...

Lugar: Minneapolis, MN | 31/10/2026 21:10:24 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

ASIC Design Engineer

to the complete ASIC design cycle — from RTL to GDSII and silicon bring-up. Interface with customers and internal...

Lugar: Fort Collins, CO | 31/10/2026 20:10:55 PM | Salario: S/. $61900 - 99000 per year | Empresa: Broadcom

Principal ASIC/SoC Architect & Design Engineer

’s components. RTL Design and Synthesis: - Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.... - Optimize RTL code for area, power, and performance. - Implement and verify complex digital blocks. Constraint Development...

Lugar: Minneapolis, MN | 31/10/2026 20:10:45 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

Senior ASIC Design Engineer - Agentic AI

that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications... RTL, and deliver a fully verified, synthesis/timing clean design. Collaborate and coordinate with other designers...

Lugar: Santa Clara, CA | 31/10/2026 20:10:10 PM | Salario: S/. No Especificado | Empresa: Nvidia