efficient DFT solutions Perform RTL coding and Verification using Verilog/System Verilog Utilize industry standard DFT tools... experience developing STA constraints for DFT modes and working directly with PD teams to close timing - Experience with RTL...
Lugar:
Austin, TX | 18/10/2026 19:10:19 PM | Salario: S/. No Especificado | Empresa:
Amazon. Finds and implements corrective measures to resolve failing tests. Collaborates with GPU architects, RTL developers...
at the ground level by modeling and estimating power at every stage of the design from early RTL to final netlist... power analysis & modelling at various stages of design (RTL to gate level netlist) Develop and maintain dashboards...
. We are looking for a Principal Technical Program Manager to own end-to-end program execution for this chip, from RTL freeze through tape-out.... Drive the weekly chip status cadence by synthesizing inputs from RTL/DV, physical design, packaging, power, infrastructure...
Lugar:
Austin, TX | 18/10/2026 02:10:04 AM | Salario: S/. No Especificado | Empresa:
Amazon and other functions within RTL and 26 Defense will develop and drive the execution of the Business Development activities for the RTL... out new technologies applicable to our customer’s needs and requirements. Along with the General Manager of RTL...
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog Recommend new tools and practices...+ years of experience developing HDL firmware for FPGA devices Demonstrated experience developing and simulating RTL designs...
Design, propose and oversee the analysis/evaluation of hardware architectures Design and code RTL modules written...
program plan—including architecture definition, RTL (Register-Transfer Level) design, Design Verification (DV) milestones...: Partner tightly with Architecture, RTL, DV, Firmware, Software, Package/Board, and Supply Chain teams to eliminate bottlenecks...
Lugar:
Palo Alto, CA | 18/10/2026 00:10:25 AM | Salario: S/. $45 - 51 per hour | Empresa:
Rivian controller / IO blocks for server-class SoCs, correlate models against RTL behavior, prototype ideas and help productize... level performance validation between RTL and performance models, ● Expertise in analyzing and debugging performance...
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog Recommend new tools and practices...+ years of experience developing HDL firmware for FPGA devices Demonstrated experience developing and simulating RTL designs...