ASIC Design Engineer - New College Grad 2026

and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural... trade-offs based on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL...

Lugar: Santa Clara, CA | 18/11/2025 18:11:14 PM | Salario: S/. $96000 - 161000 per year | Empresa: Nvidia

Digital Design Summer/Fall Co-Op (June '26 - Dec '26)

. For example, a candidate may participate in digital system architecture, block- and system-level RTL design/coding, algorithm..., etc. Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL...

Lugar: Austin, TX | 16/11/2025 18:11:08 PM | Salario: S/. No Especificado | Empresa: Skyworks

Senior Physical Design Engineer

. Key responsibilities include: Work with design teams across various disciplines such as Digital/RTL/Analog to ensure... with RTL design teams to drive assembly and design closure. Provide technical direction, coaching, and mentoring to junior...

Lugar: Burlington, VT | 15/11/2025 23:11:30 PM | Salario: S/. $90400 - 133760 per year | Empresa: Marvell

Digital Design Engineer III

, including requirements definition, RTL design, simulation, and verification. The role involves close collaboration with senior.... Implement digital designs using RTL methods (Verilog, VHDL, SystemVerilog), utilizing synthesis and AI-assisted tools...

Lugar: Colorado Springs, CO | 15/11/2025 18:11:52 PM | Salario: S/. $110800 - 139000 per year | Empresa: FRONTGRADE TECHNOLOGIES

Lead ASIC Design Engineer, Amazon Leo

job responsibilities Key job responsibilities RTL Design and development of custom blocks. Integration of large subsystems Gate... and verification engineers to validate fixes and ensure design closure. Facilitate seamless integration across Firmware, RTL...

Lugar: Austin, TX | 15/11/2025 03:11:06 AM | Salario: S/. No Especificado | Empresa: Amazon

FPGA Engineer

Responsibilities: Documents and analyses design requirements for implementation. RTL coding, simulating... and workflow, familiar with mainstream FPGAs and the development tools. Good RTL coding practices, familiar with both VHDL...

Lugar: Irvine, CA | 15/11/2025 01:11:06 AM | Salario: S/. No Especificado | Empresa: Katalyst HealthCares & Life Sciences