Principal FPGA Engineer I

and route and timing closure) and verification. Proficient in HDL coder, Modelsim RTL simulation tools, Xilinx and Microsemi...

Lugar: Austin, TX | 16/05/2026 17:05:17 PM | Salario: S/. No Especificado | Empresa: CesiumAstro

SOC Timing Analysis (STA) Engineer ,HBM

die. You will work closely with RTL design, physical design, architecture, design for test (DFT), verification, and product teams... test pattern generation (ATPG) mode constraints, MBIST timing closure, and JTAG interface timing. Partner with RTL...

Lugar: Richardson, TX | 16/05/2026 02:05:24 AM | Salario: S/. No Especificado | Empresa: Micron

Senior Design Verification Engineer - Memory Controller IP

-silicon RTL Verification activities related to Memory Controller SoftIP development, on leading-edge DDR, HBM, and GDDR DRAM... of controller RTL design Development & support of Verification environment scripting and capabilities Qualifications...

Lugar: Hillsboro, OR | 16/05/2026 02:05:25 AM | Salario: S/. No Especificado | Empresa: Rambus

MTS Verification Engineering

will participate in pre-silicon RTL Verification activities related to Rambus DRAM controller product line for controller technologies... environment, sequences, debug of controller RTL design Development & support of Verification environment scripting...

Lugar: Hillsboro, OR | 16/05/2026 02:05:54 AM | Salario: S/. $87500 - 162500 per year | Empresa: Rambus

ASIC Digital Design, Sr Manager

while remaining deeply engaged in technical execution. You bring extensive experience defining and implementing RTL and micro... directly with RTL, reviewing detailed design implementations, and guiding engineers through complex debug and convergence...

Lugar: Sunnyvale, CA | 15/05/2026 23:05:57 PM | Salario: S/. No Especificado | Empresa: Synopsys