ASIC Engineer, Physical Design

performance and power Work with the RTL design team to understand partition architecture and drive physical aspects early in the... design cycle Interface with the RTL design team to drive design modifications to resolve congestion/timing issues...

Lugar: Austin, TX - Sunnyvale, CA | 06/11/2025 00:11:52 AM | Salario: S/. No Especificado | Empresa: Meta

CPU Physical Design Engineer

design. Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS...

Lugar: Santa Clara, CA | 06/11/2025 00:11:06 AM | Salario: S/. No Especificado | Empresa: Apple

Graphics Power Analysis & Optimization Engineer

estimation, power targets and perform what-if analysis at architectural evaluation stage. - Support RTL and gate-level power... power optimizations in both RTL and gates. - Identify the best power sign-off tests to improve power analysis coverage...

Lugar: Austin, TX | 05/11/2025 20:11:26 PM | Salario: S/. No Especificado | Empresa: Apple

RFIC Layout Engineer

and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering...

Lugar: Austin, TX | 05/11/2025 20:11:52 PM | Salario: S/. No Especificado | Empresa: Apple

Graphics Power Analysis & Optimization Engineer

estimation, power targets and perform what-if analysis at architectural evaluation stage. - Support RTL and gate-level power... power optimizations in both RTL and gates. - Identify the best power sign-off tests to improve power analysis coverage...

Lugar: Austin, TX | 05/11/2025 19:11:24 PM | Salario: S/. No Especificado | Empresa: Apple