Staff Digital IC Design Engineer

, and interface functions that are protocol or standard compliant RTL implementation in SystemVerilog/Verilog of digital functions... Block-level verification including testbench creation, test plan definition, test case creation/debug, RTL and gate-level...

Lugar: Irvine, CA | 28/10/2026 20:10:38 PM | Salario: S/. $110000 - 165000 per year | Empresa: MaxLinear

FPGA IP Software Development Engineer

, and debugging FPGA-based systems for embedded, networking, and acceleration applications. This role is primarily focused on FPGA RTL..., and validate RTL for FPGA-based systems and platforms. Implement and integrate FPGA subsystems various I/0 Technologies (PCIe...

Lugar: San Jose, CA | 28/10/2026 19:10:58 PM | Salario: S/. No Especificado | Empresa: Altera

Silicon Electrical Engineer

and silicon-based systems. Design, implement, and optimize RTL code using SystemVerilog and Verilog while ensuring performance..., or digital design development environments. Strong expertise in RTL design and development utilizing SystemVerilog and Verilog...

Lugar: San Francisco, CA | 28/10/2026 19:10:35 PM | Salario: S/. No Especificado | Empresa: Akkodis

Chip Lead

, planning, dependencies, and risk mitigation. Collaborate across architecture, RTL, verification, physical design, validation... processes. PREFERRED EXPERIENCE Strong ASIC/SoC development experience across multiple areas, such as architecture, RTL...

Lugar: Santa Clara, CA | 28/10/2026 19:10:21 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

GPU Design Verification Engineer

of our innovative graphics IP. By collaborating closely with architects, RTL developers, and physical design teams, your contributions...

Lugar: Folsom, CA | 28/10/2026 18:10:33 PM | Salario: S/. No Especificado | Empresa: Intel

Design Verification Engineer, New Grad

, and recovery, and work with architects, RTL designers, and firmware engineers. About the Role As a new grad Design Verification... regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out. Responsibilities...

Lugar: San Jose, CA | 28/10/2026 18:10:27 PM | Salario: S/. $120000 - 150000 per year | Empresa: SambaNova

ASIC DFT Engineer - Acacia (Hybrid)

analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product... holes, chain failures, and pattern simulation issues Work with RTL and verification teams to ensure DFT requirements...

Lugar: San Jose, CA | 28/10/2026 18:10:37 PM | Salario: S/. No Especificado | Empresa: Cisco Systems