Senior Staff Design Engineer

job responsibilities include RTL design, verification, synthesis, timing optimization, static timing check, CDC check, Lint check, power..., or similar field with 10+ years of experience on digital IC design. - Experience on RTL design using System Verilog, timing...

Lugar: Santa Clara, CA | 07/05/2026 00:05:23 AM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

Eng Sr - Elec

including assisting in requirements generation and implementation, ownership of RTL coding, synthesis, place and route, timing...

Lugar: Nashua, NH | 06/05/2026 22:05:19 PM | Salario: S/. No Especificado | Empresa: BAE Systems

Senior Principal Engineer Digital ASIC Design/Manager

to I/O and analog functions. Perform RTL design, synthesis, LINT, RDC/CDC, LEC, timing constraint development, static timing analysis..., and custom RTL based hardware accelerators. Experience with architectural tradeoffs for selecting/defining high-speed...

Lugar: San Diego, CA | 06/05/2026 19:05:05 PM | Salario: S/. No Especificado | Empresa: Kyocera

Principal ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 8+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: USA | 06/05/2026 17:05:57 PM | Salario: S/. No Especificado | Empresa: SpaceX