SMTS Design Verification Engineer

that gives the team confidence in the RTL before silicon is committed. This is a full-ownership DV role. You will write the DV...-cause issues to RTL or testbench, and track bug closure through the design team. Post-Silicon Support: Provide debug...

Lugar: Minneapolis, MN | 01/05/2026 01:05:09 AM | Salario: S/. No Especificado | Empresa: Micron

Android Engineer II (Client Platform)

product expansion through robust internationalization (i18n), including right-to-left (RTL) support, while helping scale... internationalization (i18n) best practices, including RTL layout support and localization workflows Collaborate with backend and platform...

Lugar: Boston, MA | 01/05/2026 00:05:04 AM | Salario: S/. $125000 - 175000 per year | Empresa: Whoop

Principal Digital Design Engineer

-architecture and RTL for complex power management integrated circuits. Work closely with system and chip architects to design...-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans...

Lugar: San Diego, CA | 01/05/2026 00:05:26 AM | Salario: S/. $160400 - 237320 per year | Empresa: Marvell

Sr Principal Digital Design Engineer

-architecture and RTL for complex power management integrated circuits. Work closely with system and chip architects to design...-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans...

Lugar: San Diego, CA | 01/05/2026 00:05:01 AM | Salario: S/. No Especificado | Empresa: Marvell

Director of SoC Design

of progress metrics. What We're Looking For BS degree or higher in EE or CE or CS 12-15+ years or more of RTL...

Lugar: San Diego, CA | 30/04/2026 23:04:48 PM | Salario: S/. No Especificado | Empresa: Marvell

Staff Manager - SoC Design

7+ years or more of RTL experience 1 + years of experience managing a design team Demonstrated ability to lead...

Lugar: San Diego, CA | 30/04/2026 22:04:40 PM | Salario: S/. $145400 - 215340 per year | Empresa: Marvell

FPGA Intern (Fall 2026)

graduated from a four-year university, please apply to be an Associate Engineer. Role: RTL Development for FPGA targeted... converters, memories, MCUs Write software to interface and test RTL in hardware Collaborate closely with electrical...

Lugar: San Francisco, CA | 30/04/2026 22:04:35 PM | Salario: S/. $29 per hour | Empresa: Astrani

Staff Physical Design Engineer

with company-wide technology strategy Perform RTL-to-GDSII implementation for multiple SoC programs, including synthesis... design flow, RTL integration, synthesis, and timing closure highly preferred Strong knowledge of modern EDA tools and flows...

Lugar: Irvine, CA | 30/04/2026 21:04:24 PM | Salario: S/. $112300 - 166280 per year | Empresa: Marvell

Design Verification (DV) Engineer

flexible environment Writing detailed verification plans Quickly root-cause RTL bugs Collaborating directly with designers... Professional experience (2+ years) in RTL functional verification for FPGA or ASIC Experience with code and functional coverage...

Lugar: USA | 30/04/2026 21:04:37 PM | Salario: S/. $175000 - 250000 per year | Empresa: Hudson River Trading