challenges affecting PCB layouts to ensure robustness. Develop synthesizable RTL code using Verilog or VHDL, create test benches.... Expertise in HDL programming (Verilog and/or VHDL) for synthesizable RTL and verification. Experience with FPGAs and SoCs...
challenges affecting PCB layouts to ensure robustness. Develop synthesizable RTL code using Verilog or VHDL, create test benches.... Expertise in HDL programming (Verilog and/or VHDL) for synthesizable RTL and verification. Experience with FPGAs with AMD Zynq...
capture, decomposition, and traceability. Develop RTL design code and simulation in VHDL, Verilog, and/or System Verilog... experience or an Advanced Degree in a related field and minimum 3 years of experience. Experience writing RTL and test benches...
-Functional Debug: Partner closely with RTL design, architecture, and software teams to root-cause and rapidly resolve functional...
Lugar:
Sunnyvale, CA | 26/04/2026 17:04:40 PM | Salario: S/. $98040 - 154800 per year | Empresa:
Astreya. Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog...
and technical leads to align priorities, manage dependencies, and support effective decision-making across circuit design, RTL... across circuit design, RTL, physical design, and design verification Hands-on experience partnering closely with engineering teams...
simulation environments (UVM/SystemVerilog/Python) to verify RTL/firmware designs and develop automated scripts for testing...
. Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog...
. Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog...
. Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog...