Digital Design Engineer

complex functional and behavioral models of the systems using Matlab/Simulink, Verilog-AMS, etc. Perform RTL design..., synthesis, timing closure, scan pattern generation, power optimization and supervise the RTL-to-GDS flow. Define the digital...

Lugar: San Diego, CA | 17/04/2026 17:04:40 PM | Salario: S/. No Especificado | Empresa: Syntiant

FPGA Silicon Design Engineer

future of the FPGA industry. About the Role Join Altera as an FPGA Silicon Design Engineer focused on RTL design.... In this role, you will be responsible for developing high-quality logic designs and RTL implementations for next-generation FPGA...

Lugar: San Jose, CA | 17/04/2026 02:04:53 AM | Salario: S/. No Especificado | Empresa: Altera

Senior Staff Digital Design Engineer

: Design and implement digital subsystems and IP blocks for mixed-signal ICs from architecture through tape-out. Develop RTL... knowledge of Verilog RTL design. Solid understanding of the digital design flow, including: Microarchitecture and RTL...

Lugar: USA | 17/04/2026 02:04:49 AM | Salario: S/. No Especificado | Empresa: Cirrus Logic

Senior ASIC DV Engineer

metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design...

Lugar: San Jose, CA | 17/04/2026 02:04:47 AM | Salario: S/. No Especificado | Empresa: Broadcom

Senior Circuit Design Engineer, DRAM

verification Design IP using RTL or custom methodologies and guide layout and verification teams Collaborate with standards, CAD... circuits with STA compliance RTL design experience Experience building architectural or behavioral models Demonstrated...

Lugar: Boise, ID | 17/04/2026 01:04:07 AM | Salario: S/. No Especificado | Empresa: Micron

Digital Design Engineer

: Design and implement digital subsystems and IP blocks for mixed-signal ICs from architecture through tape-out. Develop RTL... design experience. Master's with 0+ years of relevant experience. Strong working knowledge of Verilog RTL design. Solid...

Lugar: USA | 17/04/2026 01:04:49 AM | Salario: S/. No Especificado | Empresa: Cirrus Logic

Physical Design Engineer

infrastructure, automate PD flows, improve CAD infrastructure Collaborate with RTL Designers and provide Physical Design feedback..., and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on advanced...

Lugar: Austin, TX | 17/04/2026 00:04:52 AM | Salario: S/. $15000 - 27000 per year | Empresa: Etched
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