Application Engineer II SCBU
/DSPF, Spice, IC/ASIC design flow knowledge from RTL to GDSII, custom circuit analysis & design, knowledge of low power...
Lugar: Austin, TX | 19/01/2025 01:01:31 AM | Salario: S/. No Especificado | Empresa: Ansys
Senior SOC Pre-Silicon Verification Engineer- HBM Design
is successful. You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high-speed interface design, high-performance... bandwidth";is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the...
Lugar: Richardson, TX | 19/01/2025 01:01:16 AM | Salario: S/. No Especificado | Empresa: Micron
SoC Power and Performance (PnP) Manager
with architects and RTL teams to refine SoC power and performance features. Pre-Silicon Verification Guide and oversee power...
Lugar: Austin, TX | 19/01/2025 01:01:48 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Staff Engineer, Design Verification Engineer
/C++, System C, TCL/Perl/Python/shell-scripting RTL design/front-end design experience Experience with analog SV-RNM/EE...
Lugar: Austin, TX | 19/01/2025 01:01:05 AM | Salario: S/. $130000 - 178750 per year | Empresa: Analog Devices
Application Engineer DFT EDA
Engineer or related field Digital design experience and RTL coding with Verilog or VHDL or both Proven track record...
Lugar: Fremont, CA | 19/01/2025 01:01:11 AM | Salario: S/. No Especificado | Empresa: Siemens
FPGA/ASIC Design Specialist
of complex products that use FPGAs and/or ASICs to DO-254 Develop RTL utilizing a hardware description language (e.g. VHDL...
Lugar: Indianapolis, IN | 19/01/2025 01:01:08 AM | Salario: S/. $113179 - 183916 per year | Empresa: Rolls-Royce
UI Engineer
. * Testing & Quality: Use unit and integration tests (Jest, RTL, Cypress) to ensure reliability and performance of UI components..., JavaScript, CSS, Jest, RTL, Cypress, Git. Scalability Mindset: Ability to design solutions with long-term growth in mind (AWS...
Senior Engineer, Design Verification Engineer
/C++, System C, TCL/Perl/Python/shell-scripting RTL design/front-end design experience Experience with analog SV-RNM/EE...
Lugar: Austin, TX | 18/01/2025 23:01:48 PM | Salario: S/. $107200 - 147400 per year | Empresa: Analog Devices
Engineer, Design Verification
/Perl/Python/shell-scripting RTL design/front-end design experience Experience with analog SV-RNM/EE-net modeling...
Lugar: Austin, TX | 18/01/2025 22:01:21 PM | Salario: S/. $80180 - 110248 per year | Empresa: Analog Devices
CPU CDC/RDC/STA Engineer
• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions... • Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the...
Lugar: Santa Clara, CA | 18/01/2025 22:01:10 PM | Salario: S/. No Especificado | Empresa: Apple