High Speed Serdes System Design Engineer

with RTL simulations Develop, test, and debug firmware associated with physical layer functionality Lab testing and debug... in equalization techniques for wireline communication applications such as read-channel is also a very big plus. RTL coding...

Lugar: USA | 17/01/2026 01:01:19 AM | Salario: S/. $108000 - 192000 per year | Empresa: Broadcom

ASIC Design Verification Engineer

digital designs using reusable RTL methods (Verilog, VHDL, SystemVerilog) Complex computational architectures and algorithms... experience with ASIC and/or SoC design A strong background in RTL based digital IC design using Verilog/SystemVerilog Proven...

Lugar: Minneapolis, MN | 17/01/2026 01:01:06 AM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

Senior FPGA/ASIC Engineer (Onsite)

, and traceability. ASIC/FPGA/SoPC digital architecture development and design. Develop RTL design code and simulation in VHDL, Verilog... writing RTL and testbenches using VHDL, Verilog, or SystemVerilog. Experience using FPGA specific tools (e.g. Questasim...

Lugar: Cedar Rapids, IA | 17/01/2026 00:01:22 AM | Salario: S/. $82000 - 164000 per year | Empresa: Raytheon Technologies