Principal/ Sr. Principal FPGA Design Engineer

benches Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static... timing analysis, and power analysis Experience with FPGA simulation tools to verify performance of complex RTL blocks...

Lugar: Rolling Meadows, IL | 05/06/2026 17:06:28 PM | Salario: S/. $119600 - 179400 per year | Empresa: Northrop Grumman

Austin Hiring Event - Senior Principal Physical Design Engineer

and infrastructure in alignment with company-wide technology strategy Lead RTL-to-GDSII implementation for multiple SoC programs... technologies used in major foundries Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure...

Lugar: Austin, TX | 05/06/2026 01:06:07 AM | Salario: S/. No Especificado | Empresa: Marvell

ASIC Clocks Design Engineer - New College Grad 2026

Clocking topologies in RTL. Collaborate with Physical design and timing team to evaluate Clocking concerns and develop... solutions for supporting high speed Clocking. Together with other team members, we deliver clock RTL information to GPU, CPU...

Lugar: Santa Clara, CA | 05/06/2026 01:06:20 AM | Salario: S/. $100000 - 166750 per year | Empresa: Nvidia

CPU Verification Engineer

. In this role, you will collaborate with architects, RTL developers, and physical design teams to verify and validate cutting-edge... measures to resolve test failures Collaborate closely with CPU architects and RTL designers to verify complex architectural...

Lugar: Austin, TX | 04/06/2026 23:06:18 PM | Salario: S/. No Especificado | Empresa: Intel