Design Engineer

. Responsibilities: Perform PPA optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post... and analyze reports of ASIC flows (Synthesis, PD, Power, Timing) Implement some blocks at RTL and UPF Ability to document...

Lugar: Sunnyvale, CA | 10/01/2026 23:01:50 PM | Salario: S/. No Especificado | Empresa: Aditi Consulting

Store Manager

with RTL and optical team. Ensures all operating policies and procedures are followed at the highest level to include...

Lugar: Meriden, CT | 10/01/2026 23:01:48 PM | Salario: S/. No Especificado | Empresa: EssilorLuxottica

Hardware Design Engineer 5

within the last 3 years. Advanced knowledge of UVM and System Verilog programming languages. Basic knowledge of Verilog RTL...

Lugar: Redmond, WA | 10/01/2026 22:01:22 PM | Salario: S/. No Especificado | Empresa: Actalent

UI Staff Software Engineer

UI with i18n L10n, RTL support, and locale-aware formatting, resilient across browsers devices Experience with micro...

Lugar: Bellevue, WA | 10/01/2026 22:01:53 PM | Salario: S/. $131600 - 210300 per year | Empresa: Visa

DFT Application Engineer

Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM...

Lugar: Chandler, AZ | 10/01/2026 21:01:26 PM | Salario: S/. No Especificado | Empresa: Intel

Regional Field Manager

:** Premium Retail Services, LLC **Req ID:** 19490 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...

Lugar: Philadelphia, PA | 10/01/2026 20:01:06 PM | Salario: S/. $56000 - 60000 per year | Empresa: Acosta

Staff Engineer, Digital Design Engineering

/ SystemVerilog RTL including clock domain crossings, timing constraints and synthesis. Good understanding of the full digital flow... from RTL to GDS, including supporting place and route, LEC, STA and power analysis tasks Knowledge of Design For Test...

Lugar: Edinburgh - Freer, TX | 10/01/2026 20:01:06 PM | Salario: S/. No Especificado | Empresa: Analog Devices