CPU Architecture Performance Engineer (RISC V)

and compiler technology a plus Collaborate with CPU Performance Architecture and RTL team members to identify opportunities... performance model Work with RTL and design team to assess implementation cost for new features Collaborate...

Lugar: Santa Clara, CA | 03/06/2026 22:06:54 PM | Salario: S/. No Especificado | Empresa: Qualcomm

Principal Product Engineer

track record of shipping designs or product improvements. â–¸ Expert-level understanding of the full RTL-to-GDSII flow... to Have â–¸ Experience with Cadence Joules RTL Power Solution, Voltus IC Power Integrity, or Innovus-Tempus integrated signoff flows...

Lugar: San Jose, CA | 03/06/2026 21:06:32 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

Clocking Architect

with RTL, physical design, timing, and verification teams to ensure the clock architecture is correctly modeled and implemented... the full-chip CDC architecture plan: identify, classify, and document every asynchronous clock domain crossing from RTL...

Lugar: San Jose, CA | 03/06/2026 19:06:16 PM | Salario: S/. No Especificado | Empresa: Altera

Design Verification Engineer

hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading... of architectural, functional, and performance issues. Root-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet...

Lugar: Santa Clara, CA | 03/06/2026 18:06:41 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Senior ICE Emulation Design Engineer

, as well as supporting SW development. Key Responsibilities Partition and synthesize large SOC RTL designs for emulation... with RTL, DV and SW teams to resolve system level bugs Performance optimization Qualifications BS or MS degrees or higher...

Lugar: San Jose, CA | 03/06/2026 17:06:26 PM | Salario: S/. $150000 - 190000 per year | Empresa: Axiado