Digital Design Engineer I

principles to support block-level and system-level digital design activities, including RTL development and integration..., computer architecture, or SoC development. Understanding of digital design fundamentals, including RTL design, finite state...

Lugar: Austin, TX | 03/06/2026 17:06:51 PM | Salario: S/. $78750 - 146250 per year | Empresa: Silicon Labs

ASIC Physical Design Technical Lead

experience with Fullchip clock mesh and Flex-HTree methods RTL-to-GDSII implementation: Floorplan, Power Grid plan, place... and implementing incremental or transformative enhancements. Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow...

Lugar: San Jose, CA | 03/06/2026 17:06:33 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Design Engineer

Job Title: ASIC Design Engineer Job Description This role focuses on front-end RTL design for advanced image... for an image and video processing SoC. Work on front-end RTL design, focusing on CPU/GPU-style SoC architecture rather than...

Lugar: Richardson, TX | 03/06/2026 01:06:40 AM | Salario: S/. No Especificado | Empresa: Actalent

Controls Engineer

in Verilog/VHDL for RTL design, synthesis, and verification PCB layout experience using tools like Altium Designer Experience...

Lugar: USA | 03/06/2026 00:06:13 AM | Salario: S/. $130000 - 140000 per year | Empresa: Viridien

Principal Foundry Technologist

in digital design floor planning, STA;taking RTL to GDS and optimize for PPA Some experience in coding using various languages...

Lugar: Redmond, WA | 03/06/2026 00:06:40 AM | Salario: S/. No Especificado | Empresa: Microsoft

CPU Power Analysis Engineer

. Power characterization of various CPU benchmarks using tools like PTPX and Joules. Work closely with RTL design... implementation techniques in RTL, Synthesis or Physical design stages. Low power intent concepts and languages (UPF or CPF...

Lugar: Austin, TX | 03/06/2026 00:06:49 AM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

Engineering Director - Verification IP

Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters... ï¬eld from reputed institute · 18+ years of working experience in RTL design, IP/VIP development/veriï¬cation or emulation...

Lugar: Austin, TX | 02/06/2026 21:06:23 PM | Salario: S/. $180400 - 250000 per year | Empresa: Siemens