track record of shipping designs or product improvements. â–¸ Expert-level understanding of the full RTL-to-GDSII flow... to Have â–¸ Experience with Cadence Joules RTL Power Solution, Voltus IC Power Integrity, or Innovus-Tempus integrated signoff flows...
and compiler technology a plus Collaborate with CPU Performance Architecture and RTL team members to identify opportunities... performance model Work with RTL and design team to assess implementation cost for new features Collaborate...
you will: · Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models...
and research. Roles and Responsibilities Collaborate with CPU Performance Architecture and RTL team members to identify... architectural performance model Work with RTL and design team to assess implementation cost for new features Collaborate...
for FPGA designs. Create detailed RTL (VHDL/Verilog/SystemVerilog) and accompanying constraints to meet timing, power...
hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading... of architectural, functional, and performance issues. Root-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet...
closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule. Solve... Verilog RTL and make minor modifications for timing or power. Knowledge of digital circuits, high speed flops, synchronizers...
, icvalidator or calibre, UPF, RTL, SPICE, OASIS, and ODB++. Experience with physical Design including at least 2 of the following...
coverage tracking, and functional coverage tracking Testbench development for the verification of RTL blocks using VHDL... to start date RTL coding and simulation in VHDL or Verilog Testbench development for the verification of RTL blocks using...
-architecture, RTL, and physical design starting with specification. Using AI agents to process large data and existing codebase..., evaluation frameworks to measure agent accuracy. Experience with System Verilog, RTL and hardware description language...