SoC Small Cores Engineering Program Manager
/FW lineage for these custom cores in a SW simulated environment and in the respective RTL code environment...
Lugar: Beaverton, OR | 25/12/2024 00:12:19 AM | Salario: S/. No Especificado | Empresa: Apple
Physical Design Methodology Engineer for High Performance / Low Power Designs
and guard bands Drive IP physical implementation recipes from synthesis to route to achieve the best performance/watt RTL...
Lugar: Austin, TX | 24/12/2024 21:12:54 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Research Analyst
by managing own activities. May lead small projects under the supervision of an RTL/CMD. 9. Exhibits a positive attitude...
Lugar: Arlington, VA | 24/12/2024 18:12:27 PM | Salario: S/. No Especificado | Empresa: CNA
Licensed Store Manager
monthly Store Visit Form for review with RTL and optical team. Ensures all operating policies and procedures are followed...
Lugar: San Leandro, CA | 23/12/2024 03:12:57 AM | Salario: S/. No Especificado | Empresa: EssilorLuxottica
Senior ASIC Integration and CAD Engineer
strategies, and custom routing Guide internal RTL designers in closing timing, reducing congestion, optimizing power consumption... to mass production Expertise in synthesis and static timing analysis Required strengths Integrating RTL modules...
Lugar: Santa Clara, CA | 22/12/2024 18:12:14 PM | Salario: S/. $120000 - 193500 per year | Empresa: Palo Alto Networks
Senior ASIC Integration and CAD Engineer
strategies, and custom routing Guide internal RTL designers in closing timing, reducing congestion, optimizing power consumption... to mass production Expertise in synthesis and static timing analysis Required strengths Integrating RTL modules...
Lugar: Santa Clara, CA | 22/12/2024 02:12:00 AM | Salario: S/. $120000 - 193500 per year | Empresa: Palo Alto Networks
CPU Gate Level Synthesis/Verification Engineer
design team in block level verification runs and debug • Running synthesis on the RTL to find potential gate-level issues... Knowledge of RTL-to-gate formal verification tools (LEC) and debug techniques, low power structural verification tools (VCLP...
Lugar: Santa Clara, CA | 22/12/2024 01:12:38 AM | Salario: S/. No Especificado | Empresa: Apple
Hardware Design Engineering Intern/ Co-Op (Graduate | Summer 2025 | Hybrid)
Participate in RTL design in Verilog Synthesis with timing driven placement and design for power (DFP) Floorplanning... Some other tasks that we may assign you will include analysis of logical equivalent check (LEC), RTL clocking analysis, static power...
Lugar: Santa Clara, CA | 22/12/2024 01:12:05 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
CPU Gate Level Synthesis/Verification Engineer
design team in block level verification runs and debug • Running synthesis on the RTL to find potential gate-level issues... should possess CPU implementation and verification experience Knowledge of RTL-to-gate formal verification tools (LEC) and debug...
Lugar: Santa Clara, CA | 21/12/2024 23:12:18 PM | Salario: S/. No Especificado | Empresa: Apple
Tools Product Applications Engineer
debuggers Experience in RTL and C coding Experience analyzing simulation or logic analyzer waveforms Outstanding...
Lugar: Longmont, CO | 21/12/2024 23:12:25 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices