R&D Engineer IC Design 4

implementation flow from RTL synthesis, timing analysis / closure. · Requires proficiency with the following design tools / flows...: · TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler...

Lugar: USA | 16/01/2026 19:01:08 PM | Salario: S/. No Especificado | Empresa: Broadcom

Emulation Engineer

You Are Your responsibilities are as follows but not limited to: Builds emulation and FPGA models and solutions from RTL design using synthesis... to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development...

Lugar: Austin, TX | 16/01/2026 18:01:45 PM | Salario: S/. No Especificado | Empresa: Intel