Digital Design Engineer

block specification, block level simulation, documentation Implementation: RTL design in Verilog, lint, clock domain... of relevant digital/ASIC/IC design experience for Bachelor's Degree Knowledge of RTL coding in Verilog and/or VHDL Knowledge...

Lugar: Agoura Hills, CA | 24/11/2025 01:11:03 AM | Salario: S/. $83400 - 154800 per year | Empresa: Rambus

Senior FPGA Design Engineer

Senior FPGA Engineer – Bay Area CA About the Job You’re Considering Hands-on experience with RTL design and Vivado.... Develop and implement RTL and FPGA methodologies for robust designs. Work confidently with lab equipment and ensure smooth...

Lugar: San Jose, CA | 23/11/2025 03:11:18 AM | Salario: S/. $88800 - 166398 per year | Empresa: Capgemini

Senior Emulation Methodology Engineer

for next-generation products. Work on advanced hardware/software tools that improve RTL validation, debugging, and accelerate product...). Knowledge of CPU/GPU architecture and protocols such as PCIe, DRAM, Ethernet, AMBA, and CXL. Experience in RTL design...

Lugar: Austin, TX | 23/11/2025 00:11:00 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

CPU Verification Engineer

architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural...

Lugar: Austin, TX | 22/11/2025 20:11:56 PM | Salario: S/. $90890 - 170890 per year | Empresa: Intel