Sr. FPGA Design Engineer

interfaces. Responsibilities: As a member of the FPGA Design Team, you will be responsible for the design and delivery of RTL... responsibilities include: Design and development of RTL modules based on high-level requirements Make enhancements to existing IPs...

Lugar: Austin, TX | 10/01/2025 03:01:33 AM | Salario: S/. No Especificado | Empresa: Trend Micro

Electrical Engineer, Digital ASIC design

level digital implementation. In this position you will do the following: - Verilog RTL-level digital designs, debug... skills Basic RTL coding and documentation practices Verilog (preferred) or VHDL fluency in design, simulation...

Lugar: Plantation, FL | 10/01/2025 01:01:45 AM | Salario: S/. No Especificado | Empresa: Motorola Solutions

ASIC Design Engineer - Pixel IP

Qualifications Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog. Extensive shown...

Lugar: Cupertino, CA | 09/01/2025 20:01:31 PM | Salario: S/. No Especificado | Empresa: Apple

DFT Engineer

logic scan test You will work with Physical Designers to validate the DFT timing constraints You will work with RTL... vendor tools Have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power...

Lugar: Mountain View, CA | 09/01/2025 19:01:46 PM | Salario: S/. No Especificado | Empresa: Enfabrica