Intern - HBM System Engineer
with Linux Experience with RTL modeling using Verilog or SystemVerilog Experience programming and debugging FPGAs...
FPGA/ASIC Design Engineer
that use FPGAs and/or ASICs to DO-254 standards. Develop RTL using hardware description languages (e.g., VHDL, Verilog...
Lugar: Indianapolis, IN | 08/01/2025 20:01:31 PM | Salario: S/. No Especificado | Empresa: Talascend
Silicon Power Architect
design principles across RTL, design and system level. Preferred Qualifications MSEE or PhD equivalent. Experience...
Lugar: San Diego, CA - Sunnyvale, CA | 08/01/2025 19:01:14 PM | Salario: S/. No Especificado | Empresa: Meta
SoC Design Verification Engineer - NPU
verification tests. Debug test failures to determine the root cause;work with RTL and firmware engineers to resolve design... knowledge. Proficient in debugging firmware and RTL code using simulation tools. Proficient in developing and using UVM...
Lugar: Boxborough, MA | 08/01/2025 03:01:31 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Senior Design Verification Engineer
and random verification tests. Debug test failures to determine the root cause;work with RTL engineers to resolve design.... Proficient in debugging RTL code using simulation tools. Proficient in using UVM testbenches and working in Linux and Windows...
Lugar: Boxborough, MA | 08/01/2025 02:01:42 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
FPGA Design Engineer
Responsibilities Drive RTL development and testing for FPGA targets/platforms to support rapid prototyping Partner with Design... (RTL, Simulation, Implementation, Hands on bring-up and debug) Experience with commercial HDL simulators (Modelsim...
Lugar: Sunnyvale, CA | 08/01/2025 00:01:22 AM | Salario: S/. No Especificado | Empresa: Meta
FPGA Developer
Strong analytical and problem solving skills More than 3 years of relevant professional experience Proven FPGA RTL development...
Lugar: Boise, ID | 08/01/2025 00:01:47 AM | Salario: S/. No Especificado | Empresa: Idaho Scientific
ASIC Design Engineer
analysis on suggested architecture(s) and algorithm(s) Perform RTL design and logic implementation of agreed architecture...
Lugar: Cupertino, CA | 08/01/2025 00:01:39 AM | Salario: S/. No Especificado | Empresa: Apple
Chip Engineering Lead
and modeling, RTL design, verification, emulation, physical design, tapeout, post-silicon bringup and qualification... audiences and customers. â— Years of expertise developed as an individual contributor in chip RTL design, verification...
Lugar: Mountain View, CA | 08/01/2025 00:01:41 AM | Salario: S/. No Especificado | Empresa: Enfabrica
ASIC Design Engineer
analysis on suggested architecture(s) and algorithm(s) Perform RTL design and logic implementation of agreed architecture...
Lugar: Cupertino, CA | 07/01/2025 22:01:16 PM | Salario: S/. No Especificado | Empresa: Apple