Internship - Design Engineering

Design Team for Xtensa processors. Responsibilities include RTL implementation of microprocessor cores, multiprocessor sub...-systems, and their peripherals. Tasks involve implementing micro-architecture in Verilog RTL, simulating and debugging...

Lugar: San Jose, CA | 27/02/2025 18:02:35 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

Sr. Advanced ASIC/VLSI Design Engineer

using RTL coding languages such as Verilog or VHDL. Collaborate with system architects to define design requirements... and specifications. Develop and optimize RTL code for performance, power, and area. Perform functional and timing simulations to ensure...

Lugar: Plymouth, MN | 27/02/2025 18:02:42 PM | Salario: S/. No Especificado | Empresa: Honeywell