Physical IC Design Engineer

, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out..., and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies;preferable in-depth...

Lugar: San Jose, CA | 11/12/2025 03:12:51 AM | Salario: S/. No Especificado | Empresa: Broadcom

DFT IC Design Engineer

, this position will require in-depth knowledge and expertise towards DFT related aspects of IC Design through RTL and netlists... with BISR, BIST, MBIST, SCAN, ATE, ATPG Hierarchical DFT Flow and Methodology Development Collaborating with IC Design RTL...

Lugar: San Jose, CA | 11/12/2025 03:12:06 AM | Salario: S/. No Especificado | Empresa: Broadcom

Staff Engineer Digital Signal Processing

Automotive Ethernet/SerDes research and development with Design and simulation Provide the DSP spec and RTL validation support... Correction theory is a plus Familiar with MATLAB and C++ languages RTL coding is plus #WeAreIn for driving decarbonization...

Lugar: San Jose, CA | 11/12/2025 02:12:23 AM | Salario: S/. No Especificado | Empresa: Infineon

Senior Principal Engineer

efficiency. Provide technical leadership in RTL development, synthesis, timing closure, and integration of DSP blocks into SoCs...-architecture development, RTL design (SystemVerilog/Verilog), and verification using UVM. -- ASIC design flow: floorplanning...

Lugar: Colorado | 11/12/2025 02:12:54 AM | Salario: S/. $166500 - 246420 per year | Empresa: Marvell

Physical IC Design Engineer

, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out..., and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies;preferable in-depth...

Lugar: San Jose, CA | 11/12/2025 00:12:32 AM | Salario: S/. No Especificado | Empresa: Broadcom

Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 10/12/2025 23:12:52 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 10/12/2025 22:12:16 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom