Application Engineer II SCBU

/DSPF, Spice, IC/ASIC design flow knowledge from RTL to GDSII, custom circuit analysis & design, knowledge of low power...

Lugar: Austin, TX | 16/01/2025 21:01:36 PM | Salario: S/. No Especificado | Empresa: Ansys

ASIC Design Engineer - Hardware

, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs... IP and support projects by applying the performance monitoring system Run and debug RTL checks to ensure design quality...

Lugar: Austin, TX | 16/01/2025 20:01:13 PM | Salario: S/. No Especificado | Empresa: Nvidia

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM. - Write RTL...

Lugar: Austin, TX | 16/01/2025 20:01:30 PM | Salario: S/. No Especificado | Empresa: Apple

Vice President, R&D Aprisa

). Responsibilities: Develop and implement a competitive digital RTL-to-GDSII solution for the DDCP business and portfolio of products..., including RTL synthesis, place and route, and static timing analysis. Develop and implement capabilities for multi-die design...

Lugar: Fremont, CA | 16/01/2025 19:01:58 PM | Salario: S/. No Especificado | Empresa: Siemens

ASIC Design Engineer, Technical Leader

and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help... and waveform debug experience. Experience resolving setup and hold timing violations with RTL modification. Experience developing...

Lugar: San Jose, CA | 16/01/2025 18:01:34 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Design Engineer, Senior Technical Leader

and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help... with RTL modification. Experience developing micro-architecture solutions and RTL implementation. Preferred Qualifications...

Lugar: San Jose, CA | 16/01/2025 18:01:38 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Sr. Physical Design Engineer

as the full-chip level from RTL to GDSII. You will collaborate with the Foundry Process Engineer, SoC Architect.... In-Depth Knowledge of design flow from RTL to GDSII. Good knowledge of EM-IR sign-off requirements. Experience in using EDA...

Lugar: Palo Alto, CA | 16/01/2025 18:01:24 PM | Salario: S/. $66.34 per hour | Empresa: Belcan