Sr. Design Verification Engineer, Silicon and Systems Group

, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex... for stimulus and corner-case scenarios Participate in test plan and coverage reviews Drive complex RTL and TB debugs Drive UPF...

Lugar: Sunnyvale, CA | 03/04/2026 18:04:45 PM | Salario: S/. No Especificado | Empresa: Amazon

ASIC Engineering Technical Leader

Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical... in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the...

Lugar: San Jose, CA | 03/04/2026 17:04:13 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Sr. ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 5+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: USA | 03/04/2026 17:04:44 PM | Salario: S/. No Especificado | Empresa: SpaceX

ASIC Engineering Technical Leader - DFT

in San Jose with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams... role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design...

Lugar: San Jose, CA | 03/04/2026 17:04:07 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Engineering Technical Leader - DFT

Technical Lead in San Jose, with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical... in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the...

Lugar: San Jose, CA | 03/04/2026 17:04:44 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Design Engineer (Onsite)

-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Lead design... from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes...

Lugar: San Jose, CA | 03/04/2026 17:04:44 PM | Salario: S/. No Especificado | Empresa: Cisco Systems