Sales Manager - Wireless
:** Premium Retail Services, LLC **Req ID:** 18856 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
Lugar: Carbondale, IL | 30/12/2025 22:12:26 PM | Salario: S/. $45000 - 50000 per year | Empresa: Acosta
R&D IC Design Engineer
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design for test...
Lugar: Irvine, CA | 30/12/2025 22:12:03 PM | Salario: S/. No Especificado | Empresa: Broadcom
District Manager - Wireless
, LLC **Req ID:** 18749 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
Lugar: Lubbock, TX | 30/12/2025 21:12:00 PM | Salario: S/. $75000 - 85000 per year | Empresa: Acosta
Wireless Sales Manager - Longview, TX
:** 18883 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
Lugar: Longview, TX | 30/12/2025 20:12:36 PM | Salario: S/. $45000 - 50000 per year | Empresa: Acosta
R&D IC Design Engineer
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...
Lugar: Irvine, CA | 30/12/2025 19:12:10 PM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom
Wireless Sales Manager - Greenville, NC
:** 17950 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
Lugar: Rocky Mount, NC | 30/12/2025 19:12:10 PM | Salario: S/. $45000 - 50000 per year | Empresa: Acosta
Physical Design Engineer II (Silicon Engineering)
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design...
SOC/ASIC Physical Design Engineer II (Silicon Engineering)
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
Senior System Power Architect
, GPU, DSP, TPU) Knowledge of RTL code such as VHDL or Verilog and FPGA implementation flow (RTL, synthesis, P&R, timing...
Lugar: San Jose, CA | 29/12/2025 20:12:49 PM | Salario: S/. $175000 - 219000 per year | Empresa: Lattice Semiconductor