Research Analyst

by managing own activities. May lead small projects under the supervision of an RTL/CMD. 9. Exhibits a positive attitude...

Lugar: Arlington, VA | 24/12/2024 18:12:27 PM | Salario: S/. No Especificado | Empresa: CNA

Senior ASIC Integration and CAD Engineer

strategies, and custom routing Guide internal RTL designers in closing timing, reducing congestion, optimizing power consumption... to mass production Expertise in synthesis and static timing analysis Required strengths Integrating RTL modules...

Lugar: Santa Clara, CA | 22/12/2024 18:12:14 PM | Salario: S/. $120000 - 193500 per year | Empresa: Palo Alto Networks

Senior ASIC Integration and CAD Engineer

strategies, and custom routing Guide internal RTL designers in closing timing, reducing congestion, optimizing power consumption... to mass production Expertise in synthesis and static timing analysis Required strengths Integrating RTL modules...

Lugar: Santa Clara, CA | 22/12/2024 02:12:00 AM | Salario: S/. $120000 - 193500 per year | Empresa: Palo Alto Networks

CPU Gate Level Synthesis/Verification Engineer

design team in block level verification runs and debug • Running synthesis on the RTL to find potential gate-level issues... Knowledge of RTL-to-gate formal verification tools (LEC) and debug techniques, low power structural verification tools (VCLP...

Lugar: Santa Clara, CA | 22/12/2024 01:12:38 AM | Salario: S/. No Especificado | Empresa: Apple

CPU Gate Level Synthesis/Verification Engineer

design team in block level verification runs and debug • Running synthesis on the RTL to find potential gate-level issues... should possess CPU implementation and verification experience Knowledge of RTL-to-gate formal verification tools (LEC) and debug...

Lugar: Santa Clara, CA | 21/12/2024 23:12:18 PM | Salario: S/. No Especificado | Empresa: Apple

Principal DTCO Engineer: Block level PPA - TPG

RTL to GDS flow for PPA analysis Providing actionable feedback to technology and design rule teams to help reach block... with RTL to GDS flow for technology development Track record of Si technology understanding and of innovation in the DTCO...

Lugar: Boise, ID | 21/12/2024 21:12:16 PM | Salario: S/. No Especificado | Empresa: Micron

ASIC Design Engineer

RTL design, synthesis, functional verification and timing analysis using innovative CAD tools and using the latest process...

Lugar: Santa Clara, CA | 21/12/2024 21:12:12 PM | Salario: S/. No Especificado | Empresa: Nvidia