R&D IC Design Engineer

, RTL/gate level simulations & silicon debugging scripting for various IC design tasks such as STA, equivalency checks... and problem solving skills as well as hands-on lab debugging experiences Good knowledge of RTL simulation and synthesis...

Lugar: Irvine, CA | 31/12/2025 02:12:15 AM | Salario: S/. No Especificado | Empresa: Broadcom

R&D IC Design Engineer

design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design for test...

Lugar: Irvine, CA | 31/12/2025 02:12:03 AM | Salario: S/. No Especificado | Empresa: Broadcom

R&D IC Design Engineer

design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...

Lugar: Irvine, CA | 31/12/2025 00:12:50 AM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom

R&D IC Design Engineer

design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...

Lugar: Irvine, CA | 30/12/2025 21:12:07 PM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom

Senior Engineer - Design for Test (DFT)

test plans and engage closely with verification engineers to perform waveform reviews. Ensure RTL quality pre-DFT to ensure... the RTL is good for DFT insertion and coverage. Hold a primary role in enabling silicon by working directly with test...

Lugar: Hillsboro, OR | 30/12/2025 19:12:15 PM | Salario: S/. No Especificado | Empresa: Microsoft