. What YOU will do: You will support requirements capture and ASIC / FPGA digital architecture. You will implement ASIC / FPGA digital design using RTL... will be subject to a government security investigation/reinstatement and must meet eligibility requirements RTL coding and simulation...
for implementation Implement design in RTL (VHDL) and perform module level simulations Perform Synthesis, Place and Route... (PAR) and Static Timing Analysis (STA) Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC...
documents. – Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend... with FPGAs (Xilinx, Altera, etc.). – 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design. – 3+ years...
of functionality in a CPU design, you will have the responsibilities as follows: • Work closely with architecture and RTL designers...
/equalization techniques, signal integrity, power integrity). Ability to dig into RTL or FW code supporting the custom circuit...
RTL in support of active projects Develop FPGA-based solutions for pre-silicon and post-silicon validation Evaluation...
manufacturing, ASIC RTL, FPGA BS, etc. Experience performing techniques including SCA, FIA, AOI, NIR Inspection, EOFM, EOP, XRAY...
of functionality in a CPU design, you will have the responsibilities as follows: • Work closely with architecture and RTL designers...
in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis...
, review, and validate RTL in support of active projects Design and debug FPGA-based validation boards for pre- and post...