Senior Video Design Engineer

-architecture and RTL to meet performance, area, and power requirements Reviewing linting, synthesis, CLP, CDC, and DV coverage... and managing multiple tasks Principal duties: RTL implementation using Verilog/SystemVerilog Design optimization for power...

Lugar: San Diego, CA | 20/12/2025 21:12:24 PM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

Sr. ASIC Design Engineer (Silicon Engineering)

, performance requirements and system limitations Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate... in RTL implementation PREFERRED SKILLS AND EXPERIENCE: Ability to solve complex problems including clock domain...

Lugar: USA | 20/12/2025 18:12:41 PM | Salario: S/. No Especificado | Empresa: SpaceX

(Senior) Engineer, DSP Systems Engineering, meoSphere

into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms - RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...

Lugar: Long Beach, CA | 20/12/2025 03:12:42 AM | Salario: S/. $150000 - 190000 per year | Empresa: SES S.A.

Store Manager

with RTL and optical team. Ensures all operating policies and procedures are followed at the highest level to include...

Lugar: Atwater, CA | 19/12/2025 22:12:43 PM | Salario: S/. $68640 - 112477.04 per year | Empresa: EssilorLuxottica