(Senior) Engineer, DSP Systems Engineering, meoSphere

into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms — RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...

Lugar: Long Beach, CA | 19/12/2025 18:12:51 PM | Salario: S/. $150000 - 190000 per year | Empresa: SES

Store Manager

with RTL and optical team. Ensures all operating policies and procedures are followed at the highest level to include...

Lugar: Atwater, CA | 19/12/2025 18:12:39 PM | Salario: S/. $68640 - 112477.04 per year | Empresa: EssilorLuxottica

Financial Operations Analyst

. has a track record of originating $1.5+ billion of residential transition loans (RTL) to real estate investors through its... vehicle for current and future RTL originations. About the Role: This position supports the Capital Markets team...

Lugar: Texas | 19/12/2025 18:12:35 PM | Salario: S/. No Especificado | Empresa: Vontive

Senior Digital Design Engineer

logic required to implement new products in a wide range of application spaces RTL digital design and problem solving... such as linear regulators, DC-DC converters, data converters, and mixed signal processing functions. RTL design for synchronous...

Lugar: Chandler, AZ | 19/12/2025 03:12:59 AM | Salario: S/. No Especificado | Empresa: Analog Devices

ASIC Digital Design Engineer

, I/O, power consumption, area utilization, recurring cost and security functions. Implement and simulate IP blocks in RTL using... architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal...

Lugar: Boise, ID | 19/12/2025 01:12:45 AM | Salario: S/. No Especificado | Empresa: Idaho Scientific

Senior Circuit Design Engineer

clocking, and power management solutions. Drive the design and physical implementation of custom digital IPs from RTL..., etc..) is a plus. Experience with RTL, logic synthesis and verification is a plus. Mixed signal circuit design experience...

Lugar: Santa Clara, CA | 19/12/2025 01:12:02 AM | Salario: S/. No Especificado | Empresa: Nvidia

Senior/Principal ASIC Digital Design Engineer

, recurring cost and security functions. Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages... methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification...

Lugar: Boise, ID | 19/12/2025 00:12:09 AM | Salario: S/. No Especificado | Empresa: Idaho Scientific

ASIC Design Engineer, GPU/ML Shader Core

for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean... requirements PREFERRED EXPERIENCE: Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML...

Lugar: Santa Clara, CA | 18/12/2025 19:12:31 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices