Eng Sr Prin II - Elec
requirements management, RTL design, verification, synthesis, timing analysis, lab bring up/validation Experience working...
requirements management, RTL design, verification, synthesis, timing analysis, lab bring up/validation Experience working...
and digital designers. Create DSP and FEC hardware block specifications appropriate for RTL implementation. Perform research...
using Vivado, IP Integrator, and Vitis. Develop RTL modules in VHDL/Verilog for Zynq PL or Xilinx FPGA. Build...
within verification teams, providing feedback to RTL designers and IP architects. Requirements SystemVerilog/UVM expertise... constructive feedback to, FE RTL design teams and CPU/IP micro-architects. Proficiency with industry-standard EDA simulation...
in environments that require cross-domain expertise. You have deep technical knowledge in RTL , Firmware, and system-level modeling.../control features and ensure alignment with firmware and RTL implementation Develop and maintain software models for system...
interfaces. The program is already in motion, and a specialized 60/40 RTL Engineering – DV team is being built to accelerate... infrastructure. Strong proficiency in RTL/Verilog/SystemVerilog, microarchitecture, synthesis, timing constraints, and lint/CDC...
development from architecture definition, RTL design, Verification, IP design, Physical design, silicon bring up, test...
applications. Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL... or Perl) to enhance power analysis efficiency. Collaboration: Working with other teams, including RTL, Architecture, Physical...
, or bounded proofs with sufficient coverage. Drive formal tools to realize their best performance. Debug RTL to identify... Verilog HDLs and able to understand sophisticated RTL quickly. Experience with formal tools and knowledge of formal...
closely with RTL & DFT designers Strong TCL/Python scripting knowledge required, Perl is a plus. Good debug skill...