Power Management Design Engineer

development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD... Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains Familiar...

Lugar: San Diego, CA | 26/11/2025 18:11:36 PM | Salario: S/. No Especificado | Empresa: Qualcomm

Principal/ Senior Principal Digital ASIC Circuit Design Engineer

circuits. Must be proficient in Verilog, System Verilog or VHDL RTL coding, write functional test benches and have a thorough... is a plus. Must have strong written and oral communication skills. Responsibilities: Circuit behavioral coding in Verilog, System Verilog or VHDL RTL...

Lugar: USA | 26/11/2025 18:11:20 PM | Salario: S/. $119600 - 179500 per year | Empresa: Northrop Grumman

ASIC Methodology Engineer

with version control tools like Perforce or Git Experience with place & route tools and a good understanding of the ASIC RTL-GDSII...

Lugar: San Diego, CA | 26/11/2025 01:11:33 AM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm

ASIC Design Engineer - New College Grad 2025

team, detailing, implementing, and delivering verified RTL to meet design targets. Analyze architectural trade-offs based... on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL, and deliver a fully...

Lugar: Santa Clara, CA | 26/11/2025 00:11:05 AM | Salario: S/. $96000 - 161000 per year | Empresa: Nvidia

Digital Design Engineer

block specification, block level simulation, documentation Implementation: RTL design in Verilog, lint, clock domain... of relevant digital/ASIC/IC design experience for Bachelor's Degree Knowledge of RTL coding in Verilog and/or VHDL Knowledge...

Lugar: Agoura Hills, CA | 23/11/2025 19:11:03 PM | Salario: S/. $83400 - 154800 per year | Empresa: Rambus