Wireless SOC FW Engineer
team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration...
Lugar: San Francisco, CA | 29/10/2025 01:10:06 AM | Salario: S/. No Especificado | Empresa: Apple
ASIC Design and Integration Engineer
. Responsibilities Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog... industry experience Preferred Qualifications Experience: 8+ years of proven experience in ASIC design, including RTL...
Lugar: Cupertino, CA | 29/10/2025 01:10:39 AM | Salario: S/. No Especificado | Empresa: Apple
CPU Design Verification Engineer
responsibilities: • Work closely with architecture and RTL designers on verifying the functionality correctness of the design • Develop...
Lugar: Santa Clara, CA | 29/10/2025 01:10:05 AM | Salario: S/. No Especificado | Empresa: Apple
CPU Processor Power Management Verification Engineer
with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop...
Lugar: Santa Clara, CA | 29/10/2025 01:10:14 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple
CPU Design Timing Engineer
implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure... fundamental timing paths Working knowledge of clock-domain crossing and reset-domain crossing Experience with RTL modeling...
Lugar: Santa Clara, CA | 29/10/2025 00:10:41 AM | Salario: S/. No Especificado | Empresa: Apple
CPU Gate Level Synthesis Engineer
-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running RTL to gate level... with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, RTL optimization...
Lugar: Santa Clara, CA | 29/10/2025 00:10:33 AM | Salario: S/. No Especificado | Empresa: Apple
CPU Design Verification Engineer
responsibilities: • Work closely with architecture and RTL designers on verifying the functionality correctness of the design • Develop...
Lugar: Santa Clara, CA | 29/10/2025 00:10:07 AM | Salario: S/. No Especificado | Empresa: Apple
CPU Processor Power Management Verification Engineer
with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop...
Lugar: Santa Clara, CA | 29/10/2025 00:10:30 AM | Salario: S/. No Especificado | Empresa: Apple
RFIC Design Engineer
spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...
Lugar: Los Angeles, CA | 28/10/2025 23:10:22 PM | Salario: S/. No Especificado | Empresa: Apple
Wireless SOC FW Engineer
team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration...
Lugar: Los Angeles, CA | 28/10/2025 23:10:14 PM | Salario: S/. No Especificado | Empresa: Apple