RFIC Design Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...

Lugar: Los Angeles, CA | 28/10/2025 23:10:00 PM | Salario: S/. $120300 - 181200 per year | Empresa: Apple

CPU Design Verification Engineer

responsibilities as follows: • Work closely with architecture and RTL designers on verifying the functionality correctness of the...

Lugar: Santa Clara, CA | 28/10/2025 23:10:13 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

ASIC Design and Integration Engineer

. Description Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog..., Computer Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design, including RTL design...

Lugar: Cupertino, CA | 28/10/2025 21:10:18 PM | Salario: S/. No Especificado | Empresa: Apple

SOC Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...

Lugar: San Francisco, CA | 28/10/2025 21:10:32 PM | Salario: S/. No Especificado | Empresa: Apple

SOC Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...

Lugar: San Francisco, CA | 28/10/2025 20:10:55 PM | Salario: S/. No Especificado | Empresa: Apple

CPU DFT Verification Engineer

. Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL...

Lugar: Santa Clara, CA | 28/10/2025 20:10:25 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

FPGA Development Engineer, Annapurna Labs

beyond what is possible today. Key job responsibilities - Develop RTL designs for FPGA based acceleration;including designs running on the accelerator...

Lugar: Austin, TX | 28/10/2025 19:10:32 PM | Salario: S/. No Especificado | Empresa: Amazon

CPU Design Timing Engineer

implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure...

Lugar: Santa Clara, CA | 28/10/2025 19:10:54 PM | Salario: S/. No Especificado | Empresa: Apple