Senior Physical Design Engineer

with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis... techniques RTL to GDS methodologies and formal equivalence Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence...

Lugar: Hillsboro, OR | 25/09/2026 01:09:28 AM | Salario: S/. No Especificado | Empresa: Intel

RTL/Logic Design Engineer

from Synopsys, Cadence, and Mentor Graphics, with strong skills in simulation, synthesis, and timing analysis. This individual works... including Verilog, Timing Analysis Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics Strong...

Lugar: Santa Clara, CA | 24/09/2026 17:09:11 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Principal Digital Engineer

below: Simulation – Mentor ModelSim, Cadence Xcelium, Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus... or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus Preferred Qualifications: Advanced degree...

Lugar: Linthicum, MD | 24/09/2026 17:09:50 PM | Salario: S/. $119600 - 179400 per year | Empresa: Northrop Grumman