Senior Staff Emulation Engineer

(Python, Perl, Tcl, shell) and tooling enhancements. - Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate... offerings from leading vendors such as Synopsys, Cadence, and Siemens, with deep experience in building complex SoC...

Lugar: Santa Clara, CA | 01/08/2026 17:08:43 PM | Salario: S/. $113920 - 170600 per year | Empresa: Marvell

Synthesis-DFT Stitch CAD Engineer

, leveraging both Synopsys and Cadence solutions and tools. Improving the SoC Synthesis and DFT Stitch methodologies for diverse...

Lugar: San Diego, CA | 01/08/2026 02:08:37 AM | Salario: S/. $164000 - 246000 per year | Empresa: Qualcomm

PD Engineer

cells Place & Route (PNR) tool experience on Cadence Innovus and/or Synopsys Fusion Compiler Timing closure (STA...) experience in Synopsys PTSI Function ECO implementation Formal verification (FV) experience Power domain analysis (IR Drop...

Lugar: Santa Clara, CA | 01/08/2026 02:08:46 AM | Salario: S/. $107400 - 161200 per year | Empresa: Qualcomm

STA Engineer

‑on experience with: Synopsys Prime Time Synopsys Design Compiler / Cadence Genus Preferred Qualifications Implementation...

Lugar: Santa Clara, CA | 01/08/2026 02:08:55 AM | Salario: S/. $153200 - 229800 per year | Empresa: Qualcomm

Analog Circuit Design Engineer

and methodologies, such as Synopsys and Cadence, for design and simulation You should demonstrate the following professional traits..., and understanding of foundational digital design concepts Synopsys and Cadence design tools and flows Design optimization techniques...

Lugar: Santa Clara, CA | 31/07/2026 22:07:04 PM | Salario: S/. No Especificado | Empresa: Intel