Junior Physical Design Engineer (CPU)

: Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing... Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus) Job Type: College Grad...

Lugar: Hillsboro, OR | 17/07/2026 20:07:45 PM | Salario: S/. $105650 - 149150 per year | Empresa: Intel

Principal Analog Layout Engineer

“Virtuoso VXL” and/or Synopsys “Custom Compiler” layout tools. Experienced in Mentor Graphics “Calibre” drc/lvs verification...

Lugar: San Diego, CA | 16/07/2026 22:07:15 PM | Salario: S/. $152300 - 225440 per year | Empresa: Marvell

Sr Staff Analog Layout Engineer

such as Cadence Virtuoso, Mentor Graphics, or Synopsys Custom Compiler. Virtuoso is preferred. Familiar with LVS, DRC, ERC, antenna...

Lugar: San Diego, CA | 16/07/2026 18:07:24 PM | Salario: S/. $129100 - 191030 per year | Empresa: Marvell