Physical Design Engineer

with industry-standard physical design and signoff tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, Fusion Compiler...

Lugar: San Jose, CA | 25/09/2026 22:09:39 PM | Salario: S/. $105000 - 120000 per year | Empresa: Altera

Principal ASIC Design Engineer

. ### Synthesis & Timing Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA...

Lugar: Boise, ID | 25/09/2026 22:09:23 PM | Salario: S/. No Especificado | Empresa: Micron

Principal ASIC/SoC Design Engineer

’s components. RTL Design and Synthesis: - Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.../MSEE or equivalent 10+ years of direct industry experience with ASIC and/or SoC design. Proficiency in Synopsys Design...

Lugar: Minneapolis, MN | 25/09/2026 22:09:44 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

Physical Design CAD Engineer

foundries. Working knowledge of configuring and developing flow automation using EDA tools such as Synopsys Fusion Compiler...

Lugar: Hillsboro, OR | 25/09/2026 18:09:06 PM | Salario: S/. No Especificado | Empresa: Microsoft

Applications Engineer- SiC in Advanced Packaging

training for Wolfspeed sales teams, foundry partners, and EDA ecosystem players (e.g., Cadence, Synopsys) on SiC design rules... to packaging (e.g., Cadence Sigrity, Synopsys) is a plus. Strong oral and written communication and presentation skills. The...

Lugar: North Carolina | 25/09/2026 17:09:23 PM | Salario: S/. No Especificado | Empresa: Wolfspeed