Principal DFT Engineer (Silicon Engineering)
netlist DFT implementation Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path...
netlist DFT implementation Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path...
, and embedded systems Perform and support digital circuit analysis throughout various stages of the design lifecycle (RTL, netlist...
-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects... such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist...
issues. Waveform & Silicon Analysis: Collect and analyze waveforms, run analog simulations, and review RTL/netlist...
, timing closure, lower power implementation and netlist quality check with RTL designer and PD team. Work on SDC development...
designs and test environments while supporting netlist bring-up, design validation, and silicon characterization activities...
logic synthesis. Implement checks to develop high quality netlist for P&R. Run STA and review design quality from timing...
Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist). Understanding of SOC clocking and reset methodology...
(CI) pipelines to ensure PDK updates do not break legacy designs or connectivity logic. Netlist & Connectivity: Own the logic... for netlist extraction, ensuring that the connectivity graph generated by the code perfectly matches the physical intent...
techniques to correlate electrical characterization with design netlist and layout, supporting both design verification...