SoC Design Engineer
Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis...
Lugar: Santa Clara, CA | 08/04/2026 17:04:36 PM | Salario: S/. $110600 - 140000 per year | Empresa: OmniVision
Principal ASIC Design Verification Engineer (Starshield)
languages, e.g. Python for automation RTL design, chip bring-up, and post-silicon validation experience Ability to work...
Sr. ASIC Design Engineer (Starshield)
. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 5+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...
Principal Electrical Engineer - ASIC/FPGA Mission Systems (Onsite)
Technologies team. What You Will Do: Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing... issued SECRET security clearance is required prior to start date RTL coding and simulation in VHDL or Verilog Digital...
Lugar: El Segundo, CA | 07/04/2026 22:04:08 PM | Salario: S/. No Especificado | Empresa: Raytheon Technologies
ASIC Verification Engineer
Define, develop, and automate flows and methodologies to efficiently build, deploy, and verify generated RTL Ensure code... and functional coverage of all the RTL which you will verify Build verification components using SV/UVM methodology Driving...
Lugar: Austin, TX | 07/04/2026 18:04:22 PM | Salario: S/. $116000 - 189750 per year | Empresa: Nvidia
Senior Engineer
circuits. Experience with tools/skill sets to include: Software Defined Radios (RTL-SDR, HackRF or the like), RFID analysis...
Lugar: Baltimore, MD | 05/04/2026 23:04:37 PM | Salario: S/. No Especificado | Empresa: TechINT Solutions Group
Analog-Mixed Signal Design Engineer
, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock...
Lugar: Santa Clara, CA | 04/04/2026 22:04:32 PM | Salario: S/. $105000 - 140000 per year | Empresa: OmniVision
Distinguished Engineer - Memory Subsystem Center of Excellence (CoE), Custom Silicon
for architecture, micro‑architecture, RTL, DV, PHY integration, and system validation decisions. Define and maintain reference... across multiple programs and sites. Guide cross‑functional teams (architecture, RTL, DV, PHY, FW/SW, validation) to deliver reusable...
Lugar: Santa Clara, CA | 04/04/2026 21:04:27 PM | Salario: S/. No Especificado | Empresa: Marvell
Mgr II- Eng Elec
architecture and design tradeoffs Experienced in all stages of FPGA and/or ASIC development including requirements management, RTL...
Lugar: Manchester, NH | 04/04/2026 19:04:56 PM | Salario: S/. No Especificado | Empresa: BAE Systems
Staff Design Verification Engineer/Architect, HBM
(schematic-based) or RTL design verification flows Demonstrated ability to independently define and drive verification...
Lugar: Richardson, TX | 04/04/2026 19:04:26 PM | Salario: S/. No Especificado | Empresa: Micron