Digital ASIC Design Engineer for Mixed-Signal IPs

General Summary: The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the... flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor...

Lugar: San Diego, CA | 09/04/2026 22:04:02 PM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm

FPGA Engineer

with RTL simulation tools (Questasim) Familiarity with advanced FPGA platforms (MPSoC, RFSoC, Ultrascale+, Versal, Stratix...

Lugar: Tewksbury, MA | 09/04/2026 17:04:58 PM | Salario: S/. $80000 - 190000 per year | Empresa: FishEye Software

Sr. Member Technical Staff - DEG DRAM Design

occupation. Position requires: 1\. Memory design;2\. High-speed clocking and interface development;3\. RTL to GDS design... (code synthesizable RTL, code TCL constraints, Design Compiler, PrimeTime, LEC, and UPF);4\. Custom circuit design...

Lugar: Folsom, CA | 09/04/2026 17:04:52 PM | Salario: S/. No Especificado | Empresa: Micron

Sentinel - Systems Engineer

/Verilog), implementing designs using RTL. Ability to show self as team player, able to multi-task, able to generate quality...

Lugar: USA | 08/04/2026 17:04:25 PM | Salario: S/. $79300 - 118900 per year | Empresa: Northrop Grumman

Principal ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 10+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: USA | 08/04/2026 17:04:57 PM | Salario: S/. No Especificado | Empresa: SpaceX