Senior FPGA Engineer

expectations Required skills FPGA design experience including thorough design documentation, completion and review of RTL... blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design Ability...

Lugar: Englewood, CO | 04/04/2026 17:04:07 PM | Salario: S/. $130000 - 185000 per year | Empresa: SEAKR Engineering

Sr. FPGA Engineer

activities such as requirements generation, design, RTL-synthesis, test bench development and design simulation, static timing...

Lugar: USA | 04/04/2026 17:04:00 PM | Salario: S/. No Especificado | Empresa: Innovim Technology Solutions

Sr. ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 5+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: USA | 04/04/2026 17:04:06 PM | Salario: S/. No Especificado | Empresa: SpaceX

Sr. Design Verification Engineer, Silicon and Systems Group

, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex... for stimulus and corner-case scenarios Participate in test plan and coverage reviews Drive complex RTL and TB debugs Drive UPF...

Lugar: Sunnyvale, CA | 04/04/2026 02:04:57 AM | Salario: S/. No Especificado | Empresa: Amazon