like PCIE, CXL, AXI, CHI will be useful. Experience and knowledge in architecture, RTL design, performance analysis and power...
and 20+ years of relevant industry experience. We seek individuals with expert design experience to understand RTL design... analysis and optimizations using advanced synthesis techniques and RTL design improvement for optimal area, timing and power...
Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...
Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...
to model performance and power. Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout... between performance and power. Post-silicon bring-up, debug and identify issues on emulator and RTL. Understanding of ASIC design...
: Strong understanding of the complete IC design flow, from front-end design (RTL, synthesis, simulation) to back-end physical implementation...
, and performance targets. - Develop detailed specifications for the chip’s components. RTL Design and Synthesis: - Use Synopsys... Design Compiler to create RTL (Register Transfer Level) designs. - Optimize RTL code for area, power, and performance...
Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...
Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...
. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints... for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them...