hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading... of architectural, functional, and performance issues. Root-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet...
, icvalidator or calibre, UPF, RTL, SPICE, OASIS, and ODB++. Experience with physical Design including at least 2 of the following...
Lugar:
Phoenix, AZ | 03/06/2026 23:06:33 PM | Salario: S/. No Especificado | Empresa:
Intel-architecture, RTL, and physical design starting with specification. Using AI agents to process large data and existing codebase..., evaluation frameworks to measure agent accuracy. Experience with System Verilog, RTL and hardware description language...
track record of shipping designs or product improvements. ▸ Expert-level understanding of the full RTL-to-GDSII flow... to Have ▸ Experience with Cadence Joules RTL Power Solution, Voltus IC Power Integrity, or Innovus-Tempus integrated signoff flows...
you will: · Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models...
with uArchitecture, RTL coding, FPGA optimization for timing & power, simulation, and validation Preferred Qualifications - 6+ years...
Lugar:
Redmond, WA | 03/06/2026 21:06:56 PM | Salario: S/. No Especificado | Empresa:
Amazon closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule. Solve... Verilog RTL and make minor modifications for timing or power. Knowledge of digital circuits, high speed flops, synchronizers...
and compiler technology a plus Collaborate with CPU Performance Architecture and RTL team members to identify opportunities... performance model Work with RTL and design team to assess implementation cost for new features Collaborate...
performance and power goals are met on schedule. Partner closely with architecture, RTL design, verification, firmware, system...
with RTL, physical design, timing, and verification teams to ensure the clock architecture is correctly modeled and implemented... the full-chip CDC architecture plan: identify, classify, and document every asynchronous clock domain crossing from RTL...
Lugar:
San Jose, CA | 03/06/2026 19:06:57 PM | Salario: S/. No Especificado | Empresa:
Altera