experience (RTL, Simulation, Implementation, Hands on bring-up and debug)Experience with commercial HDL simulators (Modelsim... experience8+ years of end-to-end FPGA design experience (RTL, Simulation, Implementation, Hands on bring-up and debug)Experience...
Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...
, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering...
and crypptographic solutions for embedded communication systems Experience with Mentor Graphics Verification tools FPGA/ASIC RTL Design...
Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...
Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...
in optical networking and digital ASIC development. Primary Duties and responsibilities: RTL design and verification...
Lugar:
Pittsford, NY | 18/01/2025 02:01:03 AM | Salario: S/. No Especificado | Empresa:
Ciena will be responsible for implementing complex digital designs from RTL to GDSII, with a focus on optimizing for power, performance...
Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...
members - Familiar with Synopsys Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level... a plus DFT experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate...