Agentic AI Engineer

, and tool-calling specs that feed Cadence agents the right design context (RTL, scripts, logs, reports, methodology docs) at the... Pipelines. Curate, clean, and label datasets from EDA artifacts (RTL, waveforms, logs, reports, schematics). Build synthetic...

Lugar: USA | 04/06/2026 18:06:26 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

Austin Hiring Event - Senior Staff Physical Design Engineer

is available for qualified candidates. Key responsibilities include: Work with design teams across various disciplines such as Digital/RTL... tools Work with RTL design teams to drive assembly and design closure. Provide technical direction, coaching...

Lugar: Austin, TX | 04/06/2026 18:06:21 PM | Salario: S/. $132500 - 196140 per year | Empresa: Marvell

ASIC Design Engineer

I'm currently hiring for Hardware Engineer opportunity in the Dallas, TX area! This role focuses on front-end RTL... and SystemVerilog blocks for an image and video processing SoC. Work on front-end RTL design, focusing on CPU/GPU-style SoC...

Lugar: Richardson, TX | 04/06/2026 18:06:49 PM | Salario: S/. No Especificado | Empresa: Actalent

FPGA Development Tools Engineer – Synthesis

of FPGA compilation technology. In this role, you will develop and enhance synthesis capabilities that transform RTL designs... strong expertise in RTL design and synthesis, combined with a solid software engineering background and a passion for building scalable...

Lugar: San Jose, CA | 04/06/2026 17:06:23 PM | Salario: S/. No Especificado | Empresa: Altera

Hardware Design Expert - Fully Remote

. Position: Expert Hardware / RTL Engineer – SystemVerilog / Verilog Type: Contract Compensation: $110–190/hour Location...: Remote Commitment: 20–40 hours/week Role Responsibilities Apply RTL expertise to evaluate technical tasks against real...

Lugar: New York City, NY | 04/06/2026 17:06:56 PM | Salario: S/. No Especificado | Empresa: Mercor

ASIC Engineering Technical Leader- DFT

in San Jose with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams... role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design...

Lugar: San Jose, CA | 04/06/2026 17:06:16 PM | Salario: S/. No Especificado | Empresa: Cisco Systems