SoC Digital Design Engineer, Multimedia Lab

(Power, Performance, Area) evaluation during the early design phase. - RTL Implementation: Write high-quality, well...-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation. - Front-End Quality Control: Perform Lint...

Lugar: San Jose, CA | 03/04/2026 22:04:38 PM | Salario: S/. No Especificado | Empresa: TikTok

Senior SoC Digital Design Engineer, Multimedia Lab

(Power, Performance, Area) evaluation during the early design phase. - RTL Implementation: Write high-quality, well...-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation. - Front-End Quality Control: Perform Lint...

Lugar: San Jose, CA | 03/04/2026 21:04:22 PM | Salario: S/. No Especificado | Empresa: TikTok

Senior FPGA Engineer

and experiences to apply. Performance Objectives and Responsibilities: Develop, implement and maintain RTL FPGA design..., logic analyzer and ILA. Proven ability to lead FPGA design reviews and present complex RTL, timing, and integration...

Lugar: Santa Clara, CA | 03/04/2026 21:04:36 PM | Salario: S/. No Especificado | Empresa: Johnson & Johnson

Staff SoC Design Engineer

This role focuses on SoC microarchitecture, RTL design, and full-chip integration for high-performance designs. The position... and specification through RTL development, integration, and design sign-off — in close collaboration with verification, physical design...

Lugar: Santa Clara, CA | 03/04/2026 20:04:42 PM | Salario: S/. $113920 - 170600 per year | Empresa: Marvell

Software Engineer - Cosultant

coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Role... 15+ years of working experience in RTL design, IP/VIP development/verification or emulation experience with industry...

Lugar: Austin, TX | 03/04/2026 18:04:52 PM | Salario: S/. No Especificado | Empresa: Siemens