Eng Sr - Elec
with digital logic simulation tools (e.g. QuestSim, Xcelium) and fixed point modeling for RTL verification Programming Skills...
Lugar: Falls Church, VA | 30/10/2026 19:10:26 PM | Salario: S/. No Especificado | Empresa: BAE Systems
VLSI Physical Design Engineer
-standard EDA tools, such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, or Formality, and/or Cadence RTL Compiler...
Lugar: Fort Collins, CO | 30/10/2026 19:10:26 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
Physical Designer Engineer, Synthesis/PnR
-chip level from RTL to GDSII. You will collaborate with the Foundry Process Engineer, SoC Architect, Microarchitecture...-end design team to address timing, congestion and power issues. In-Depth Knowledge of design flow from RTL to GDSII...
Lugar: Palo Alto, CA | 30/10/2026 19:10:25 PM | Salario: S/. No Especificado | Empresa: Rivian
CPU Physical Design Engineer
of CPU designs from RTL to GDSII. You will gain hands-on experience with industry-standard EDA tools and develop expertise... physical design and verification flows for custom CPU designs, ranging from RTL synthesis to GDS generation, custom and memory...
Lugar: Austin, TX | 30/10/2026 19:10:28 PM | Salario: S/. No Especificado | Empresa: Intel
Principal FPGA Emulation Engineer
with our silicon RTL and DSP architects, you will bring their designs up on FPGA to validate real-time digital, mixed-signal, and power...-control architectures pre-silicon - proving out control loops, catching RTL issues early, and de-risking tape-out. These...
Lugar: Austin, TX | 30/10/2026 18:10:18 PM | Salario: S/. No Especificado | Empresa: Renesas Electronics
CAD Design Enablement TPM
. Design and verification methodologies. RTL quality, lint, clock and reset domain crossing (CDC/RDC), constraints, simulation..., power, equivalence and signoff;front-end/back-end handoffs;early power, performance and area (PPA) estimation and RTL...
Lugar: Austin, TX | 30/10/2026 18:10:47 PM | Salario: S/. No Especificado | Empresa: Ericsson
Principal/Sr Principal Engineer Systems
/Verilog), implementing designs using RTL Ability to show self as team player, able to multi-task, able to generate quality...
Lugar: USA | 30/10/2026 18:10:21 PM | Salario: S/. $98400 - 147600 per year | Empresa: Northrop Grumman
Static Timing Analysis Engineer
Strong understanding of ASIC design flows, including RTL and place-and-route. Excellent problem-solving skills and attention...
Lugar: San Jose, CA | 30/10/2026 18:10:18 PM | Salario: S/. No Especificado | Empresa: Quest Global
Silicon CAD Technical Product Manager
. Design and verification methodologies. RTL quality, lint, clock and reset domain crossing (CDC/RDC), constraints, simulation..., power, equivalence and signoff;front-end/back-end handoffs;early power, performance and area (PPA) estimation and RTL...
Lugar: Austin, TX | 30/10/2026 18:10:07 PM | Salario: S/. No Especificado | Empresa: Ericsson
Systems Engineer
/Verilog), implementing designs using RTL Ability to show self as team player, able to multi-task, able to generate quality...
Lugar: USA | 30/10/2026 18:10:44 PM | Salario: S/. $79300 - 118900 per year | Empresa: Northrop Grumman